Difference between revisions of "Category:How to - i2c"
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| + | I2c is a 2-wire serial 8 bit communications protocol from the old days. It is mainly used to communicate between on-board components when the design does not allow for a data and address bus. Typical components are elapsed timer chips, ee-proms, FRAM's, A/D and D/A chips. Some cpu's have the I2c hardware shift registers built in. | ||
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| + | The 2 wires are the SCL or clock wire and the SDL or data wire. The clock high to low transition is used to signal that the data wire has a stable 1/0 data value and that the receiver should shift this into the data results register. The clock line is high when the bus is idle. A special high to low transition on the clock line followed by a high to low transition on the data line signals the start of a message sequence. the end of a message sequence is a low to high transition in the data line followed by a low to high transition in the SCL line. An important aspect of this communication standard is that each device is assigned a unique 7 bit address, (oh yea the 8th bit is the Read/write indicator to complete the byte. The device address is the first byte sent in any communication. Subsequent bytes of a message depend on the device you are talking to. | ||
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| + | Because of patents that have since expired, other companies had to use slightly differnet ways to do the same thing so a very similar serial communicatinos method called SPI uses 4 wires and another called TWI uses the same 2 wires. | ||
Revision as of 20:03, 18 February 2008
Please contribute your knowledge to the gumstix community
I2c is a 2-wire serial 8 bit communications protocol from the old days. It is mainly used to communicate between on-board components when the design does not allow for a data and address bus. Typical components are elapsed timer chips, ee-proms, FRAM's, A/D and D/A chips. Some cpu's have the I2c hardware shift registers built in.
The 2 wires are the SCL or clock wire and the SDL or data wire. The clock high to low transition is used to signal that the data wire has a stable 1/0 data value and that the receiver should shift this into the data results register. The clock line is high when the bus is idle. A special high to low transition on the clock line followed by a high to low transition on the data line signals the start of a message sequence. the end of a message sequence is a low to high transition in the data line followed by a low to high transition in the SCL line. An important aspect of this communication standard is that each device is assigned a unique 7 bit address, (oh yea the 8th bit is the Read/write indicator to complete the byte. The device address is the first byte sent in any communication. Subsequent bytes of a message depend on the device you are talking to.
Because of patents that have since expired, other companies had to use slightly differnet ways to do the same thing so a very similar serial communicatinos method called SPI uses 4 wires and another called TWI uses the same 2 wires.
