USB

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Revision as of 21:05, 11 November 2009 by Searchworks (Talk | contribs) (correct links)

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USBH_PWR1 Over-current fault indicator (input, active low)
USBH_PEN1 Power enable USB port (output)
USBH_P1 USB port USB D+
USBH_N1 USB D-
V_BATT USB VBUS
GND USB DGND


The 24-pin flex connector] connector has USB Host port 1 on it. USB Host port 2 is on the 60-pin Hirose connector.

The pinouts you need for USB Host port 1 are:


  • V_BATT (pin 24) - USB power
  • USBH_N1 (pin 18) - USB D-
  • USBH_P1 (pin 17) - USB D+
  • GND (pin 8) - USB Ground


In addition, you need to pull USBH_PWR1 (pin 20) up to 3.3 volts to enable the port (this is a hack, USBH_PEN1 and USBH_PWR1 should be routed to a power switch IC -for example TPS2041B- to power the USB port and monitor over-current/short-circuit conditions). You need to provide a stable 3.3 volt supply, which is fairly simple to do by adding a small SOT23 package voltage regulator (like the LM3480), with the power input coming from V_BATT (pin 24) and the output going to USBH_PWR1 (pin 20).


USBH_N1 and USBH_P1 (D-/D+) require 15K pull-down resistors each, 10-25 ohm series resistors and 68-75pF capacitors. ESD protection/transient suppression is recommended (example: SN65220 single port transient suppressor).


Refer to the PXA270 Design Guide, P. 202 (link on the bottom of this page) for more information.


USB Client

For those users attempting to get USB Client capability on their verdex-pro computer, it appears that the right signals are not brought out on any expansion. I cannot verify this absolutely for myself - but the docomentation appears to agree with my experience. I have been testing with a console-st I/O board. Here's the details being discussed as recently as January 2009.


Examples

File:24pin-connector-usb-example.png

USB Host example without ESD and over-current protections (not fully USB-compliant)



Related

PXA270 Design Guide, P. 202

Universal Serial Bus Revision 2.0 specification

Open HCI—Open Host controller Specification for USB

Implementing the Physical Layer in a USB 2.0 Compliant System, AN-5052, Fairchild Semiconductor



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